K20P144M120SF3_1210 Datasheet, PDF (30/86 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol
J_{cyc_fll}
t_{fll_acquire}
f_{pll_ref}
f_{vcoclk_2x}
f_vcoclk
f_{vcoclk_90}
I_pll
I_pll
I_pll
I_pll
t_{pll_lock}
Description
Min.
FLL period jitter
—
• f_VCO = 48 MHz
• f_VCO = 98 MHz
—
FLL target frequency acquisition time
—
PLL0,1
PLL reference frequency range
8
VCO output frequency
180
PLL output frequency
90
PLL quadrature output frequency
90
PLL0 operating current
• VCO @ 180 MHz (f_{osc_hi_1} = 32 MHz, f_{pll_ref}
—
= 8 MHz, VDIV multiplier = 22)
PLL0 operating current
• VCO @ 360 MHz (f_{osc_hi_1} = 32 MHz, f_{pll_ref}
—
= 8 MHz, VDIV multiplier = 45)
PLL1 operating current
• VCO @ 180 MHz (f_{osc_hi_1} = 32 MHz, f_{pll_ref}
—
= 8 MHz, VDIV multiplier = 22)
PLL1 operating current
• VCO @ 360 MHz (f_{osc_hi_1} = 32 MHz, f_{pll_ref}
—
= 8 MHz, VDIV multiplier = 45)
Lock detector detection time
—
J_{cyc_pll} PLL period jitter (RMS)
• f_vco = 180 MHz
—
• f_vco = 360 MHz
—
Typ.
180
150
—
—
—
—
—
2.8
Max.
—
—
1
16
360
180
180
—
4.7
—
2.3
—
3.6
—
—
100 × 10^-6
+ 1075(1/
f_{pll_ref})
100
—
75
—
J_{acc_pll}
PLL accumulated jitter over 1µs (RMS)
• f_vco = 180 MHz
• f_vco = 360 MHz
—
600
—
—
300
—
Unit
ps
ms
MHz
MHz
MHz
MHz
mA
mA
mA
mA
s
ps
ps
ps
ps
Notes
6
7
7
7
7
8
9
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δf_{dco_t}) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
K20 Sub-Family Data Sheet, Rev. 4, 10/2012.
30
Freescale Semiconductor, Inc.