K20P144M120SF3_1210 Datasheet, PDF (68/86 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Peripheral operating requirements and behaviors
Table 47. SDHC switching specifications over the full operating voltage range (continued)
Num
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
Symbol
fpp
fpp
fpp
f_OD
t_WL
t_WH
t_TLH
t_THL
t_OD
t_ISU
t_IH
Description
Min.
Max.
Clock frequency (low speed)
0
400
Clock frequency (SD\SDIO full speed)
0
25
Clock frequency (MMC full speed)
0
20
Clock frequency (identification mode)
0
400
Clock low time
7
—
Clock high time
7
—
Clock rise time
—
3
Clock fall time
—
3
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid)
-5
6.5
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC input setup time
5
—
SDHC input hold time
1.3
—
Unit
kHz
MHz
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
SD3
SD2
SD1
SD6
SD7
SD8
Figure 31. SDHC timing
6.8.11 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
K20 Sub-Family Data Sheet, Rev. 4, 10/2012.
68
Freescale Semiconductor, Inc.