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K20P144M120SF3_1210 Datasheet, PDF (48/86 Pages) Freescale Semiconductor, Inc – K20 Sub-Family | |||
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Peripheral operating requirements and behaviors
Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
ADC
⢠ADLPC = 1, ADHSC = 0 1.2
2.4
3.9
MHz
tADACK = 1/
fADACK
asynchronous
clock source
⢠ADLPC = 1, ADHSC = 1 2.4
⢠ADLPC = 0, ADHSC = 0 3.0
4.0
5.2
6.1
MHz
fADACK
7.3
MHz
⢠ADLPC = 0, ADHSC = 1 4.4
6.2
9.5
MHz
Sample Time
See Reference Manual chapter for sample times
TUE
Total unadjusted
error
⢠12-bit modes
⢠<12-bit modes
â
±4
±6.8
LSB4
5
â
±1.4
±2.1
DNL
Differential non-
linearity
INL Integral non-
linearity
EFS Full-scale error
EQ
Quantization
error
⢠12-bit modes
⢠<12-bit modes
⢠12-bit modes
⢠<12-bit modes
⢠12-bit modes
⢠<12-bit modes
⢠16-bit modes
⢠â¤13-bit modes
â
±0.7 -1.1 to +1.9 LSB4
5
-0.3 to 0.5
â
±0.2
â
±1.0 -2.7 to +1.9 LSB4
5
-0.7 to +0.5
â
±0.5
â
-4
-5.4
LSB4
VADIN =
â
-1.4
-1.8
VDDA
5
â
-1 to 0
â
LSB4
â
â
±0.5
ENOB
Effective number 16-bit differential mode
of bits
⢠Avg = 32
⢠Avg = 4
6
12.8
14.5
â
bits
11.9
13.8
â
bits
16-bit single-ended mode
⢠Avg = 32
⢠Avg = 4
12.2
13.9
â
bits
11.4
13.1
â
bits
SINAD
Signal-to-noise
plus distortion
See ENOB
6.02 Ã ENOB + 1.76
dB
THD
Total harmonic
distortion
16-bit differential mode
⢠Avg = 32
7
â
â94
â
dB
16-bit single-ended mode
⢠Avg = 32
â
-85
â
dB
SFDR
Spurious free
dynamic range
16-bit differential mode
⢠Avg = 32
7
82
95
â
dB
16-bit single-ended mode
⢠Avg = 32
78
90
â
dB
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4, 10/2012.
48
Freescale Semiconductor, Inc.
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