33781_09 Datasheet, PDF (7/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with

ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.75V ≤ V_CC ≤ 5.25V, 9.0V ≤ V_SUPn ≤ 25V,-40°C ≤ T_A ≤ 90°C, unless otherwise
noted. Voltages relative to GND, unless otherwise noted. Typical values noted reflect the approximate mean values of the
parameter at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
BUS TRANSMITTER (DnH, DnL)
Output Bus Idle Voltage (Drop)
I_nH = -200mA, I_nL = 200mA⁽⁶⁾
Output Signal High Voltage (Differential)
-12.5mA ≤ InH ≤ 1.0mA, -1.0mA ≤ InL ≤ 12.5mA ⁽⁶⁾
V_DnD(Drop)⁽⁷⁾⁽⁸⁾
–
V
–
1.6
V_DnD
(7)
(HIGH)
V
4.175
4.5
4.825
Output Signal Low Voltage (Differential)
-12.5mA ≤ InH ≤ 1.0mA, -1.0mA ≤ InL ≤ 12.5mA⁽⁶⁾
V_DnD
(7)
(LOW)
V
1.175
1.5
1.825
Vmid, (DnH + DnL)/2 (Voltage Halfway Between Bus High Side and
Bus Low Side
V_MID⁽⁸⁾
V_SUPn/
V_SUPn/ 2
V_SUPn /
V
2 - 0.8
2 +0.8
VCM Peak to Peak (Maximum Vmid-Minimum Vmid)
For Vmid (Idle), Vmid (Signal_H), Vmid (Signal_L)⁽⁵⁾
V_CMP
0
Bus Driver Vmid Peak to Peak, (DnH+DnL)/2⁽⁵⁾
For Signal to Idle, Idle, Idle to Signal,
V_MIDPP(IDLE)
–
VmidPP(Idle)=Vmid(Max)- Vmid (Min)
Bus Driver Vmid Peak to Peak (Dnh+DnL)/2⁽⁵⁾
V_{MIDPP(SIGNAL)}
–
For Signal_H to Signal_L, Signal_L, Signal_L to Signal_H, Signal_H
VmidPP(Signal)=Vmid(Max)-Vmid(Min)
–
30
mV
–
300
mV
–
80
mV
Output High Side (DnH) Driver Current Limit
Fault Condition: DnH = 0V
Normal Operation
Fault Condition: DnH = V_SUPn
I_{CL (HIGH)}
mA
-600
–
-200
-400
–
-200
150
–
350
Output Low Side (DnL) Driver Current Limit
Fault Condition: DnL = 0V
Fault Condition: DnL = V_SUPn
I_{CL (LOW)}
mA
-350
–
-150
200
–
400
Signal mode Over-current Shutdown
l ISSD l DnH, DnL
I_SSD
20
60
mA
Disabled High Side (DnH) Bus Leakage (DnL open)
DnH = 0V
DnH = V_SUPn
Disabled Low Side (DnL) Bus Leakage (DnH open)⁽⁹⁾
DnL = 0V
DnL = V_SUPn
I_LK(HIGH)
mA
-1.0
–
1.0
-1.0
–
1.0
I_LK(LOW)
mA
-1.0
–
1.0
-1.0
–
1.0
Notes
5. Not measured in production.
6. InH=bus current at DnH, InL=bus current at DnL
7. V_DnD=V_DnH-V_DnL
8. Max V_DnD = VSUPn - 2 * V_{MID_OFFSET} - V_DnD(Drop), V_{MID_OFFSET} = |V_MID - V_SUPn / 2|
9. Worst Case Disabled Low Side Bus Leakage for DnL occurs with DnL = V_SUP and DnH = 0V. In this configuration, the DnL leakage
current can exceed 1mA. This is not measured in production.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33781
7