33781_09 Datasheet, PDF(23/44 Page) Freescale Semiconductor, Inc

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33781_09 Datasheet, PDF (23/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with

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FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

and no write will occur.

Figure 16 shows the bit encoding for 32-bit SPI0 burst

transfers when the DBUS channel is set for long words. In

this transfer, the first byte contains the address of the control

data to/from that register, and the next two bytes are the data

to/from the next numerically successive registers. In the case

of reading or writing from the addressable FIFO registers, the

1st data byte would be the DnRnH byte, the next byte would

be the DnRnL byte, and the third byte would be the

DnRnSTAT byte as shown in Figure 15. Notice that in this

case, the 4th Tx byte is donât care and is not written. If this

transfer would be sent to an address in the control register

section of the register bank, the bytes sent and returned

would be first the addressed register, and then the next

consecutive registers.

Figure 17 shows the bit encoding for 32-bit SPI0 burst

transfers when the DBUS channel is set for enhanced short

words. This transfer mode is only valid when accessing the

addressable FIFO portion of the register set. In this case, the

first byte is again the 1st address of the register to be

accessed in this read/write, the second byte contains the

upper two bits of the data to be written, and the third byte is

the lower 8-bits of data to be written. The SPI0 response

encoding begins with the 2nd byte in the transfer with the 4-

bit DBUS address of the slave, which sent the data contained

in the rest of the word. This is followed by the 10-bits of data

from the DBUS slave, and then the value in the DnRnSTAT

Although it looks like the read and write for an address are

occurring at the same time, the changes caused earlier

during the same burst would not be reflected by the data

returned, because the DnRnSTAT register is latched at CS0

going low.

Refer to the section SPI0 Register and Bit Descriptions on

page 29 for the bit descriptions in Figure 15, Figure 16, and

Figure 17.

Bit 7

Bit6

BIt5

Bit4

Bit3

Bit2

Bit1

First TX Byte

R/W

ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1

Second TX Byte

Bit 7

Bit6

BIt5

Bit4

Bit3

Bit2

Bit1

First RX Byte

Second RX Byte

Figure 15. SPI0 Communications, 16-Bit Burst Transfer Bit Definitions

Bit0

ADDR0

Bit0

Bit 7

Bit6

BIt5

Bit4

Bit3

Bit2

Bit1

Bit0

First TX Byte

R/W

ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0

Second TX Byte

D15

D14

D13

D12

D11

D10

Third TX Byte

Fourth TX Byte

Bit 7

Bit6

BIt5

Bit4

Bit3

Bit2

Bit1

Bit0

First RX Byte

Second RX Byte

D15

D14

D13

D12

D11

D10

Third RX Byte

Fourth RX Byte

SDS

RNE

ICL

FIX1

FIX0

Figure 16. SPI0 Communications, 32-Bit Burst Transfer Long Word DBUS Transfer Bit Definitions

Analog Integrated Circuit Device Data

Freescale Semiconductor

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