33781_09 Datasheet, PDF (33/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
edge of CS0 after a SPI0 write to the associated DnRnH/L
registers. It is set to 1 once the DBUS state machine
completes sending the DnRnH/L data in the buffer over the
DBUS.
If SPI0 attempts to write to a transmit register that is not
empty, the new command will be ignored.
SDS - Signal Mode Shutdown
• 0 = Bus driver is active.
• 1 = High side or low side bus driver had a current
shutdown during signal mode in this DBUS transaction.
The bus driver current is independently sensed on both the
high side and the low side of the driver during signaling mode.
This bit is set if either driver exceeds the over-current
detection threshold for greater than the delay time. In that
event, the driver is disabled (becomes high-impedance) for
the remainder of that DBUS transaction.
The MCU can use this bit along with other fault condition
bits to detect that the data in this buffer may be invalid.
RNE–Receive Register Not Empty Bit
• 0 = No new data ready.
• 1 = Data is available to be read.
This bit is set when the DBUS writes to the associated
DnRnH and DnRnL registers. The bit is cleared on the rising
edge of CS0 after a read of the DnRn STAT register. This bit
is cleared even if a SPI0 framing error occurred during the
SPI burst transfer that read the receive register.
This bit will not be set if the V_SUP voltage falls below the
low voltage detect threshold for longer than the V_SUP low
mask time during the associated bus transfer.
ICL - Idle Mode Double Current Limit Bit (Idle Mode
Shutdown)
• 0 = Idle mode current limit not active.
• 1 = Idle mode current limit active.
During Idle mode, the current limit is independently sensed
on both the high side and the low side of the bus driver. An
over-current fault condition occurs if either DnH or DnL is
within the sourcing or sinking limit (500mA). This is
characterized by both DnH and DnL voltage levels being
simultaneously at either ground or the bus voltage V_BUS.
The ICL bit is set and the drivers are disabled if either of
the following conditions are true:
• the fault condition occurs continuously for 2.5μs
• the fault condition occurs four times with 50μs or less
between occurrences
Figure 27 shows a representation of the over-current fault
condition circuitry.
LIM_DH_H
LIM_DL_H
LIM_DH_L
LIM_DL_L
Over-current Fault
Figure 27. Over-current Fault Condition for ICL Bit
Fix[0:1] - Fixed Bits
These are hard coded bits - FIX0 is always zero and FIX1
is always one. These bits are the last two bits transmitted
during the SPI message. Since their values are always fixed,
these bits enable the Main MCU software to determine if the
SPI data was shifted due to one too many, or one too few SPI
clocks.
DnCTRL REGISTER
The read/write DnCTRL register sets up conditions to be
used on the DBUS. There are four of these registers, one for
each of the buses. The bit assignments are shown in
Figure 28.
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read/Write
-
-
DLYB
DLYA
-
LOOP1 LOOP0
MS
Reset
0
0
0
0
0
0
0
0
Figure 28. Dn Control Register Bit Assignment
Each bus n has an associated DnCTRL register. This
high to IDLE voltage transition) to the start of a new DBUS
register should be written to before data is sent over its bus.
A write to the register will abort any current activity on the bus.
transaction (signaled by the start of the IDLE voltage to signal
high transition).
Any bit changes will take place on the next DBUS transaction
following the conclusion of the SPI write to the register. Refer
to the Protocol Engine section for more detail.
Table 10. DLY[B:A] Frame Spacing
DLY[B:A]–Interframe Delay for Channel n
These bits specify the minimum delay between transfer
frames on the bus as illustrated in Table 10. For example,
when DLY[B:A] is set to 00, there is a minimum of four bit
times of IDLE voltage level. The time is measured from the
end of a DBUS transaction (signaled by the start of the signal
Analog Integrated Circuit Device Data
Freescale Semiconductor
DLY[B:A]
00
01
Minimum Delay Between Frames
(Bit Times)
4
5
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