33781_09 Datasheet, PDF (34/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 10. DLY[B:A] Frame Spacing (continued)
10
6
11
8
LOOP[1:0]- LOOP MODE CONTROL
• 00, 01, 10 = Loop Mode disabled.
• 11 = Loop Mode enabled
When loop mode is enabled, the transmitter and receiver
circuits are connected within the IC. This allows data to be
passed directly through the transmit and receive circuits
without going out on the DBUS channel. When LOOP mode
is enabled, the DBUS channel is disconnected from the
transmitter and receiver circuits, so that any bus fault
conditions do not interfere with this test. Setting this bit also
disables the bus channel and clears the EN bit in the DnEN
register.
MS–Message Size for Channel n
• 0 = Long Word.
• 1 = Short Word
The Long Word will contain 16 bits of data and 0 to 8 bits
of CRC. The Short Word can be made to have between 8 and
15 bits of data and 0 to 8 bits of CRC. Long words are
generally used for configuration and setup messages. Short
words are generally used for DBUS data transactions.
DnEN REGISTER
This read/write register is used to enable or disable each
of the buses. It also allows the channel thermal shutdown and
bus driver shutdown bits to be read. The bit assignments are
shown in Figure 29.
SPI Data Bit
Read/Write
Reset
Bit 7
6
5
4
3
2
1
0
TS
ISDD
-
-
-
BSWH
BSWL
EN
(D0EN only) (D0EN only)
0
0
0
0
0
0
0
0
Figure 29. DnEN Register Bits
TS – Indicates a Thermal Shutdown on Channel n
• 0 = No thermal shutdown occurring on the Channel.
• 1 = Thermal shutdown has occurred on the Channel.
If the channel bus thermal limit is reached for either of the
channel bus drivers, the channel drivers are disabled and the
TS bit is set. There is a 4 μsec filter on Tlim to prevent false
triggering. When this bit is set, the channel registers are all
reset along with the buffer pointers. Any DBUS transfer that
was in progress is stopped.
If the shutdown occurs on channel zero, the pseudo bus
switches are also opened and the BSWH and BSWL bits are
cleared. If the thermal limit is reached on either of the pseudo
bus switches (but not on the channel zero drivers), the bus
switches are opened, only the BSWH and BSWL bits are
cleared, and no other register bits are changed.
The TS bit is cleared after a zero has been written to the
TS bit.
ISDD - Idle and Signal Mode Disable on Channel n
• 0 = Idle and signal mode are active on the Channel.
• 1 = During signaling mode, the bus driver has shut
down for sequential transactions on the Channel and
the bus drivers are now disabled (high-impedance).
If a channel high side or low side bus driver over-current
limit is reached during signaling mode in 2 consecutive
frames, the bus drivers are disabled and the ISDD bit is set.
If the condition occurs on channel zero, the pseudo bus
switches are also opened and the BSWH and BSWL bits are
cleared. In addition, the channel buffer registers are reset, the
buffer pointers are reset, and the EN bit is cleared. The
remainder of the channel registers are not changed. Any
DBUS transfer that was in progress is stopped. The ISDD bit
is cleared when the MCU writes a zero to this bit.
BSWH - Bus Switch High Enable
• 0 = Channel 0 Bus High Switch Open
• 1 = Channel 0 Bus High Switch Close
Channel 0 of the 33781 has a switch on both the high side
and the low side of the bus output driver to allow the channel
to drive two separate sets of bus wires. Through this bus
switch the bus receiver can also receive data from slaves on
both of these buses. When the BSWH bit is written as zero,
the high side bus switch will be open. When the bit is written
as a 1, the high side bus switch will be closed. Reads of this
bit show the current state of the high side bus switch.
The BSWH bit is cleared and the bus switch opened if a
channel zero thermal shutdown occurs, if the channel zero
EN bit is cleared or ISDD bit is set, or if the high side or low
side pseudo bus thermal limit is exceeded. It is necessary to
write a one to the BSWH bit to close the switch again.
BSWL - Bus Switch Low Enable
• 0 = Channel 0 Bus Low Switch Open
• 1 = Channel 0 Bus Low Switch Close
When the BSWL bit is written as zero, the low side bus
switch will be open. When the bit is written as a 1, the low side
bus switch will be closed. Reads of this bit show the current
state of the low side bus switch.
The BSWL bit is cleared and the bus switch opened, if a
channel 0 thermal shutdown occurs, if the channel zero EN
33781
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Analog Integrated Circuit Device Data
Freescale Semiconductor