33781_09 Datasheet, PDF (18/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with

FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
VSUPn VOLTAGE MONITOR
This function monitors the voltage on the V_SUPn pin. If the
voltage on the pin drops below the defined voltage threshold
for longer than the voltage threshold mask time, the 33781
will continue to send queued DBUS commands, but not set
any RNE bits in the DnSTAT registers to 1, until either the
device is reset by the RST pin or the EN bits in the DnEN
registers are first set to zero, and then to one (disabled and
then enabled). By monitoring the RNE bits the MCU will know
that communications have been disrupted and can take the
appropriate action.
Receiver LRoewcneiver Low n
Receiver HRigehceniver High n
Receiver SRuemceniver Sum n
Adder
Signal Mode Oveerr-Ccurrent n
IdleIdMleoMdeoOdOveveOer-rvcCeurru-rcrerunertnret nt n
OOvever-rteTmemp ^{pn n Over-temp n}
DSISn
DSIFn
hiZhniZn
Over-cCuurrrreenntt
OOvveerr-Tteemmpp
SSeennssee
Differennttiaall
SSigignnaal ^l
GGeenneerraattiioonn
Driver
DDnHH
DDnnLL
OOvveerrv-ovoltlataggee
CCoommmmoonn
MoMdeode
CCoorrrreeccttiioonn
Figure 11. Driver/Receiver Block Diagram
DBUS DRIVER /RECEIVER (PHYSICAL LAYER)
There are four independent differential bus driver/receiver
blocks on the 33781. These blocks translate the transmit data
to the voltage and current needed to drive the DBUS. They
also detect the response current from the slave devices and
translate that current into digital levels. These circuits can
drive their outputs to the levels listed in Table 5.
The DBUS driver/receiver block diagram is shown in
Figure 11. The circuit uses a common driver for both the Idle
and Signal modes to minimize common mode noise. The
drivers are disabled in HiZ.
During Idle mode the driver is required to supply a high
current to recharge the Slave device storage capacitors. In
both Idle and Signal modes it is required to drive the DBUS
load capacitances and control the slew rate over a wide
supply voltage range and load conditions. Current limit, over-
current shutdown and thermal shutdown are included to
protect the device from fault conditions. More information can
be found in the Protection and Diagnostic Features and SPI0
Register and Bit Descriptions sections.
To ensure stability of the bus drivers, capacitors must be
connected between each output and ground. These are the
DBUS common mode capacitors. In addition, a bypass
capacitor is required at V_SUPn. These capacitors must be
located close to the IC Pins and provide a low-impedance
path to ground.
The internal signal DSIF controls the Idle to Signalling
state change, and internal signal DSIS controls the signal
level, high or low. DSIR is the slave device response signal to
the logic. This is shown in Table 6.
Table 6. Internal Signal Truth Table
DSIF
0
DSIS
0
T_S
DSIR
DnD
0
Return Data
Signal Low
0
1
0
Return Data
Signal High
1
0
0
0
High-impedance
1
1
0
0
Idle
X
X
1
0
High-impedance
Bus wire faults on a bus do not disrupt communications on
another bus. In addition, each bus channel has independent
thermal shutdown protection. Once the channel thermal limit
is reached the bus drivers become high-impedance, the TS
bit is set to a 1 and the EN bit set to 0 in the channel DEN
register. In addition the channel address buffer registers and
pointers are reset. There is a 4 usec filter on Tlim to prevent
false triggering.
The Differential Signal Generation block converts the
DSIS signal to the DBUS differential signal voltage levels.
This differential signal is buffered and slew rate controlled by
33781
18
Analog Integrated Circuit Device Data
Freescale Semiconductor