33781_09 Datasheet, PDF (27/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
message look like the CRC bits of an 8-bit response and
almost certainly would not be correct. Because the response
is incomplete and the CRC check is probably not valid, this
response is not useful.
The long word to short word message size transition
normally only occurs after setting up the DBUS peripherals.
During address setup, a message with address 0000 is sent
to attempt to set the address of the next peripheral on the
daisy-chained bus. Before any peripherals have been
assigned an address, their bus switches are opened so the
addressing message only goes to the first peripheral in line.
As each peripheral gets an address, it closes its bus switch
so the next address assignment command can reach the next
peripheral in line on the bus. Each peripheral responds to an
address assignment only once (during the next message
after the command that set its address). After the last
peripheral has been assigned an address, any subsequent
address assignments will receive no response. When the
master MCU fails to receive a response, it knows it has
passed the last peripheral. At this point, short word messages
may be sent. The first such message will have no meaningful
response associated with it.
The first message after reset is also a special case,
because there was no previous message, therefore there will
be no meaningful response during the first message transfer.
CLK 64
MHz
RSTB
PORB
SCLK0
MOSI0
MISO0
CSB0
SCLK1
MISO1
CSB1
FREQUENCY
SPREADING and
CLOCK DIVIDERS
SPI0
control regs
enable regs
poly regs
seed regs
length regs
spread dev
spread fsel
mask ID
check pattern
test mode regs
reg pointer
bit pointer
SPI1
1/3^RD BIT CLOCK
Addressed Rx Buffer
16
data
5
stat
data
stat
data
stat
data
stat
data
stat
data 16
Addressed Tx Buffer
data
x pop
data
ptr
data
slave
data
addr
enN
abort
SPI1 Registers
data
addr
data
addr
10 data
4 addr
data
addr
data
addr
data ₁₆
stat ₄
push
pop
data
16
Loop Sel
BUS Driver/Receiver Logic
CRC
chcCehcRCekcCRkC
check
Loop
Mode
Mux
Filter
Sample
Filter
Filter
Filter
Filter
receiver lowN
receiver highN
receiver sumN
signal mode
over currentN
idle mode
over currentN
over tempN
Tx not empty
CRC
generate
DBUS XFER
STATE MACHINE
Loop Sel
DSISn
DSIFn
HZN
Misc. Functions
Filter
Filter
VSUP voltage
compare
Bus switch
over temp
Figure 23. Logic Block Diagram
LOGIC BLOCK DIAGRAM DESCRIPTION
Figure 23, Logic Block Diagram, shows a block diagram of
the major logic blocks in the IC.
SPI0
The SPI0 is a standard slave serial peripheral interface.
This interface provides two-way communications between
the IC and an MCU. The MCU can write to registers that
control the operation of the IC, and read back the conditions
in the IC using the SPI. It can also write data to be sent out
on the DBUS, and read data that was returned on the DBUS.
The register pointer and bit pointer are used to control which
registers and bits are being written to, and read from using
the SPI. Its operation is described in detail in the section
entitled SPI0 COMMUNICATIONS on page 22.
The register set consists of transmit, receive, control, and
status registers. They are written and read using the SPI0
interface, and are affected by events in the IC. Detailed
descriptions of their operation and use can be found in
section SPI0 Register and Bit Descriptions.
SPI1
The SPI1 is a slave serial peripheral interface. It operates
asynchronously to the SPI0. It uses 16-bit transfers and is
read only. The MOSI function is not implemented. SPI1 only
reads the SPI1 8 16-bit circular buffer registers.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33781
27