33781_09 Datasheet, PDF (37/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
is in the system. The Fuse Parity Error Bit is also included in
this register. The bit encoding is shown in Figure 35
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read Only
FPAR
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Reset
0
0
0
0
0
0
0
1
Figure 35. Mask ID Register Bit Assignments
FPAR – Fuse Parity Error Bit
• 0 = No fuse parity error.
• 1 = There is a fuse parity error.
Some parameters in the device are trimmed by fuses.
Since these parameters can be impacted by the state of the
fuses, a fuse parity is calculated and stored during device
manufacturing. When the device is powered up, the current
fuse parity is checked against the stored parity. If they do not
match this bit is set. This bit is also set if the part is
untrimmed.
ID[6:0] – Mask ID number
The mask ID that identifies different versions or revisions
of the device.
Check Pattern and Negative Check Pattern
RegisteRS
These read-only registers are for checking whether there
is a stuck bus bit. These registers are read as a 3 byte burst
using a standard SPI burst frame The bit encoding is shown
in Figure 36 and Figure 37
SPI Data Bit
Read
Reset
Read
Reset
Read
Reset
Bit 7
6
5
4
3
2
1
0
CKPTN23 CKPTN22 CKPTN21 CKPTN20 CKPTN19 CKPTN18 CKPTN17 CKPTN16
1
0
1
0
1
0
1
0
CKPTN15 CKPTN14 CKPTN13 CKPTN12 CKPTN11 CKPTN10 CKPTN09 CKPTN08
0
1
0
1
0
1
0
1
CKPTN07 CKPTN06 CKPTN05 CKPTN04 CKPTN03 CKPTN02 CKPTN01 CKPTN00
1
0
1
0
1
0
1
0
Figure 36. Check Pattern Registers Bit Assignments
SPI Data Bit
Read
Reset
Read
Reset
Read
Reset
Bit 7
6
5
4
3
2
1
0
NCKPTN23 NCKPTN22 NCKPTN21 NCKPTN20 NCKPTN19 NCKPTN18 NCKPTN17 NCKPTN16
0
1
0
1
0
1
0
1
NCKPTN15 NCKPTN14 NCKPTN13 NCKPTN12 NCKPTN11 NCKPTN10 NCKPTN09 NCKPTN08
1
0
1
0
1
0
1
0
NCKPTN07 NCKPTN06 NCKPTN05 NCKPTN04 NCKPTN03 NCKPTN02 NCKPTN01 NCKPTN00
0
1
0
1
0
1
0
1
Figure 37. Negative Check Pattern Registers Bit Assignments
Analog Integrated Circuit Device Data
Freescale Semiconductor
33781
37