33781_09 Datasheet, PDF (28/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SPI1 REGISTERS
An eight position circular buffer made up of 16-bit words.
Reads of these registers occur in a round robin (sequential
order with wrap around at the end) fashion. If a buffer does
not contain any data it is skipped during the round robin
sequence. More information on this buffer can be found in the
section SPI1 Communications.
RST
Asserting this pin low will cause the part to reset, forcing
registers to a known state and resetting the SPI0 and SPI1
buffer pointers. All bus activity will be halted and not allowed
to restart, and no SPI activity will be recognized until the RST
goes to a logic high level.
ADDRESSED TX BUFFER
The Addressed TX Buffer is a cyclic register set that allows
up to four transmit data packets to be stored for future
transmission on the DBUS. This is done to prevent the
overwrite of transmit data if the transmission of the previous
data has not been completed. Each buffer is a 2-byte set that
contains the high byte and low byte of a DBUS command.
The transmit buffer queue looks for the lowest register
number in the channel with data to be sent, and sends it over
the DBUS. It then checks the next sequential buffer - if there
is data to be sent it will send it. If not, that buffer will be
skipped and the next buffer sent if it contains data. If no other
buffers have data ready to be sent, the queue moves back to
the top of the buffer and continues checking until data is
available.
ADDRESSED RX BUFFER
The Addressed RX Buffer is a cyclic register set that
allows up to four responses to be stored without being
transferred to the MCU via the SPI. This is done so that data
will not be lost, even if the MCU takes time to read the
response data. Each buffer is a 3-byte set that contains the
data high byte, data low byte, and status word of a DBUS
response.
The received data from DBUS transactions is stored in the
same receive buffer number as the transmit buffer for that
transaction.
BUS DRIVER/RECEIVER LOGIC
This block controls the physical layer drivers and receive
data from the physical layer receivers. The physical layer
converts the 0V to 5.0V low power logic signals to the higher
voltage and drive levels required for the bus. It also converts
the low current (0mA to 11mA typical) loading of the response
signal from the slave to logic voltage levels, to allow the
response from the slaves to be received.
Each channel contains a CRC generator, that adds a
series of bits to each of the transmitted data words sent out
on the DBUS. The CRC bits are created from the data pattern
and are used by the slave devices to determine if one or more
of the data bits sent was in error. The detailed operation and
control of this function is covered in the section entitled CRC
GENERATION /CHECKING on page 26.
This block also checks the CRC bits that have been added
to the end of the response by the slave device. For a given
pattern of received data, a new CRC is generated and
compared to the CRC bits received. This is performed on the
received data from the bus high side, bus low side and bus
sum circuits in the bus receiver. The results of these checks,
determine if the data are valid, and whether or not the error
bit is set as shown in Table 9. This bit is read back using the
SPI during the same SPI transaction that reads the response,
in order to keep them associated with each other. The CRC
bits are removed by the IC and not seen by the MCU, when
reading the data registers. Operation of the CRC Check is
covered in the section entitled CRC GENERATION /
CHECKING on page 26.
33781
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Analog Integrated Circuit Device Data
Freescale Semiconductor