33781_09 Datasheet, PDF (10/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.75V ≤ V_CC ≤ 5.25V, 9.0V ≤ V_SUPn ≤ 25V,-40°C ≤ T_A ≤ 90°C, unless otherwise
noted. Voltages relative to GND, unless otherwise noted. Typical values noted reflect the approximate mean values of the
parameter at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
BUS TRANSMITTER
Idle-to-Signal and Signal-to-Idle Slew Rate⁽¹³⁾
t_{SLEW (IDLE)}
3.0
6.0
Signal High-to-Low and Signal Low-to-High Slew
Rate^(13),(14) (See Data Valid DSIS to DnD Timing)
t_{SLEW (SIGNAL)}
3.0
6.0
Communication Data Rate Capability⁽¹⁴⁾ (Ensured by
Transmitter Data
Valid and Receiver Delay Measurements)
D_RATE
77.1
–
Data Rate(before frequency spreading)
Signal Bit Time (1 / D_RATE)⁽¹⁴⁾
t_BIT
The Max value depends on the settings in the FSEL bits
5.0
–
DBUS Start Delay, CS0 Rising Edge to DBUS⁽¹⁴⁾
note: DLY is the inter-message delay selected in the
DnCTRL register
t_DBUSSTART2 2/3t_BIT + (DLY-2) * t_BIT –
Data Valid⁽¹³⁾
DSIF = 0.5 * V_CC to DnD Fall = 5.5 V (9V < V_SUPn < 40V)
DSIS = 0.5 * V_CC to DnD Fall = 2.8V (9V < V_SUPn < 40V)
DSIS = 0.5 * V_CC to DnD Rise = 3.2V (9V < V_SUPn < 40V)
DSIF = 0.5 * V_CC to DnD Rise = 6.5 V (9V < V_SUPn < 40V)
Signal mode Over-current Shutdown Delay⁽¹⁴⁾
Signal Low Time for Logic Zero
33.3% Duty Cycle
(2/3*t_BIT) + 10% for threshold delta
t_DVLD1
t_DVLD2
t_DVLD3
t_DVLD4
t_OC
t0_LO
–
–
–
–
3.0
0.6 * t_BIT
–
–
–
–
5.0
2/3 *
t_BIT
Signal Low Time for Logic One
66.7% Duty Cycle
(1/3*t_BIT) + 10% for threshold delta
t1_LO
0.3 * t_BIT
1/3 *
t_BIT
8.0
V/μs
8.0
V/μs
200
kbps
–
μs
μs
5/3t_BIT + (DLY-2) *
t_BIT
μs
5.3
1.0
1.0
1.0
7.0
μs
0.73 * t_BIT
μs
0.37 * t_BIT
μs
Notes
13. C = 2.8nF from DnH to DnL and 2.2nF from DnH and DnL to GND, capacitor tolerance = ±10%.
14. Not measured in production.
33781
10
Analog Integrated Circuit Device Data
Freescale Semiconductor