K52P144M100SF2V2 Datasheet, PDF (66/80 Pages) Freescale Semiconductor, Inc – K52 Sub-Family

Peripheral operating requirements and behaviors
Table 54. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage
range) (continued)
Num.
S4
S5
S6
S7
S8
S9
S10
Characteristic
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
Min.
45%
—
-1.0
—
0
20.5
0
Max.
55%
15
—
15
—
—
—
Unit
BCLK period
ns
ns
ns
ns
ns
ns
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
S1
S2
S2
S3
S4
S4
S5
S9
S7
S9
S10
S7
S8
S6
S10
S8
Figure 28. I2S/SAI timing — master modes
Table 55. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num.
S11
S12
S13
S14
S15
Characteristic
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
Min.
1.71
80
45%
5.8
2
—
Max.
3.6
—
55%
—
—
20.6
Unit
V
ns
MCLK period
ns
ns
ns
Table continues on the next page...
K52 Sub-Family Data Sheet, Rev. 1, 6/2012.
66
Preliminary
Freescale Semiconductor, Inc.
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