K52P144M100SF2V2 Datasheet, PDF (63/80 Pages) Freescale Semiconductor, Inc – K52 Sub-Family

Num
SD6
SD7
SD8
Peripheral operating requirements and behaviors
Table 51. SDHC switching specifications
(continued)
Symbol Description
Min.
Max.
Unit
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
t_OD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
t_ISU
SDHC input setup time
5
—
ns
t_IH
SDHC input hold time
0
—
ns
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
SD3
SD2
SD1
SD6
SD7
SD8
Figure 25. SDHC timing
6.8.10 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
6.8.10.1 Normal Run, Wait and Stop mode performance over a limited
operating voltage range
This section provides the operating performance over a limited operating voltage for the
device in Normal Run, Wait and Stop modes.
K52 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
63
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