K52P144M100SF2V2 Datasheet, PDF (25/80 Pages) Freescale Semiconductor, Inc – K52 Sub-Family

Symbol
J13
J14
Peripheral operating requirements and behaviors
Table 14. JTAG full voltage range electricals (continued)
Description
TRST assert time
TRST setup time (negation) to TCLK high
Min.
Max.
Unit
100
—
ns
8
—
ns
TCLK (input)
J2
J3
J3
J4
J4
Figure 5. Test clock input timing
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
J5
J6
Input data valid
J7
Output data valid
J8
J7
Output data valid
Figure 6. Boundary scan (JTAG) timing
K52 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
25
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