K52P144M100SF2V2 Datasheet, PDF (30/80 Pages) Freescale Semiconductor, Inc – K52 Sub-Family

Peripheral operating requirements and behaviors
Table 16. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
V_pp5 ^{Peak-to-peak amplitude of oscillation (oscillator}
—
0.6
—
V
mode) — low-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
—
V_DD
—
V
mode) — low-frequency, high-gain mode
(HGO=1)
Peak-to-peak amplitude of oscillation (oscillator
—
0.6
—
V
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
—
V_DD
—
V
mode) — high-frequency, high-gain mode
(HGO=1)
Notes
1. V_DD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. C_x,C_y can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, R_F is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2 Oscillator frequency specifications
Table 17. Oscillator frequency specifications
Symbol
f_{osc_lo}
f_{osc_hi_1}
f_{osc_hi_2}
f_{ec_extal}
t_{dc_extal}
t_cst
Description
Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
Min.
32
3
8
—
40
—
—
—
—
Typ.
—
—
—
—
50
750
250
0.6
1
Max.
40
8
32
50
60
—
—
—
—
Unit
kHz
MHz
MHz
MHz
%
ms
ms
ms
ms
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
K52 Sub-Family Data Sheet, Rev. 1, 6/2012.
30
Preliminary
Freescale Semiconductor, Inc.
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