K52P144M100SF2V2 Datasheet, PDF (43/80 Pages) Freescale Semiconductor, Inc – K52 Sub-Family

Peripheral operating requirements and behaviors
Table 29. 16-bit ADC with PGA operating conditions (continued)
Symbol
C_rate
Description
ADC conversion
rate
Conditions
≤ 13 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
16 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
Min.
18.484
37.037
Typ.¹
—
—
Max.
450
250
Unit
Ksps
Ksps
Notes
7
8
1. Typical values assume V_DDA = 3.0 V, Temp = 25°C, f_ADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is R_PGAD/2
5. The analog source resistance (R_AS), external to MCU, should be kept as minimum as possible. Increased R_AS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for F_in=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
6.6.1.4 16-bit ADC with PGA characteristics with Chop enabled
(ADC_PGA[PGACHPb] =0)
Table 30. 16-bit ADC with PGA characteristics
Symbol Description
I_{DDA_PGA} Supply current
I_{DC_PGA} Input DC current
Conditions
Low power
(ADC_PGA[PGALPb]=0)
Min.
Typ.¹
Max.
Unit
—
420
644
μA
A
Gain =1, V_REFPGA=1.2V,
V_CM=0.5V
Gain =64, V_REFPGA=1.2V,
V_CM=0.1V
—
1.54
—
μA
—
0.57
—
μA
Table continues on the next page...
Notes
2
3
K52 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
43
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