K52P144M100SF2V2 Datasheet, PDF (20/80 Pages) Freescale Semiconductor, Inc – K52 Sub-Family

General
Table 9. Device clock specifications (continued)
Symbol Description
f_BUS
Bus clock
FB_CLK FlexBus clock
f_FLASH
Flash clock
f_ERCLK
External reference clock
f_{LPTMR_pin} LPTMR clock
f_{LPTMR_ERCLK} LPTMR external reference clock
f_{FlexCAN_ERCLK} FlexCAN external reference clock
f_{I2S_MCLK} I2S master clock
f_{I2S_BCLK} I2S bit clock
Min.
—
—
—
—
—
—
—
—
—
Max.
4
4
1
16
25
16
8
12.5
4
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, IEEE 1588 timer, and I²C signals.
Table 10. General switching specifications
Symbol
Description
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ V_DD ≤ 2.7V
• 2.7 ≤ V_DD ≤ 3.6V
• Slew enabled
• 1.71 ≤ V_DD ≤ 2.7V
• 2.7 ≤ V_DD ≤ 3.6V
Min.
1.5
100
16
100
2
—
—
—
—
Max.
—
—
—
—
—
12
6
36
24
Table continues on the next page...
Unit
Bus clock
cycles
ns
ns
ns
Bus clock
cycles
ns
ns
ns
ns
Notes
1, 2
3
3
3
4
K52 Sub-Family Data Sheet, Rev. 1, 6/2012.
20
Preliminary
Freescale Semiconductor, Inc.
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