K52P144M100SF2V2 Datasheet, PDF (24/80 Pages) Freescale Semiconductor, Inc – K52 Sub-Family

Peripheral operating requirements and behaviors
Table 13. JTAG limited voltage range electricals (continued)
Symbol
J3
Description
TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
Max.
Unit
50
—
ns
20
—
ns
10
—
ns
J4
TCLK rise and fall times
J5
Boundary scan input data setup time to TCLK rise
J6
Boundary scan input data hold time after TCLK rise
J7
TCLK low to boundary scan output data valid
J8
TCLK low to boundary scan output high-Z
J9
TMS, TDI input data setup time to TCLK rise
J10
TMS, TDI input data hold time after TCLK rise
J11
TCLK low to TDO data valid
J12
TCLK low to TDO high-Z
J13
TRST assert time
J14
TRST setup time (negation) to TCLK high
—
3
ns
20
—
ns
0
—
ns
—
25
ns
—
25
ns
8
—
ns
1
—
ns
—
17
ns
—
17
ns
100
—
ns
8
—
ns
Symbol
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
Table 14. JTAG full voltage range electricals
Description
Operating voltage
TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
1.71
0
0
0
TCLK cycle period
1/J1
TCLK clock pulse width
• Boundary Scan
50
• JTAG and CJTAG
25
• Serial Wire Debug
12.5
TCLK rise and fall times
—
Boundary scan input data setup time to TCLK rise
20
Boundary scan input data hold time after TCLK rise
0
TCLK low to boundary scan output data valid
—
TCLK low to boundary scan output high-Z
—
TMS, TDI input data setup time to TCLK rise
8
TMS, TDI input data hold time after TCLK rise
1.4
TCLK low to TDO data valid
—
TCLK low to TDO high-Z
—
Table continues on the next page...
Max.
3.6
10
20
40
—
—
—
—
3
—
—
25
25
—
—
22.1
22.1
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
K52 Sub-Family Data Sheet, Rev. 1, 6/2012.
24
Preliminary
Freescale Semiconductor, Inc.
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