K52P144M100SF2V2 Datasheet, PDF (62/80 Pages) Freescale Semiconductor, Inc – K52 Sub-Family

Peripheral operating requirements and behaviors
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
DS10
DS15
DS13
First data
DS14
First data
DS12
Data
Data
DS9
DS11
Last data
DS16
Last data
Figure 24. DSPI classic SPI timing — slave mode
6.8.7 _I²_{C switching specifications}
See General switching specifications.
6.8.8 UART switching specifications
See General switching specifications.
6.8.9 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 51. SDHC switching specifications
Num
SD1
SD2
SD3
SD4
SD5
Symbol
fpp
fpp
fpp
f_OD
t_WL
t_WH
t_TLH
t_THL
Description
Operating voltage
Card input clock
Clock frequency (low speed)
Clock frequency (SD\SDIO full speed)
Clock frequency (MMC full speed)
Clock frequency (identification mode)
Clock low time
Clock high time
Clock rise time
Clock fall time
Table continues on the next page...
Min.
2.7
0
0
0
0
7
7
—
—
Max.
3.6
400
25
20
400
—
—
3
3
Unit
V
kHz
MHz
MHz
kHz
ns
ns
ns
ns
K52 Sub-Family Data Sheet, Rev. 1, 6/2012.
62
Preliminary
Freescale Semiconductor, Inc.
General Business Information