K30P121M100SF2V2 Datasheet, PDF (66/67 Pages) Freescale Semiconductor, Inc – K30 Sub-Family

Pinout
121 Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP
BGA
D1 PTD14
DISABLED
PTD14
SPI2_SIN
SDHC0_D6 FB_AD5
E1 PTD15
DISABLED
PTD15
SPI2_PCS1
SDHC0_D7 FB_RW_b
K3 NC
NC
NC
H4 NC
NC
NC
8.2 K30 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
1
A
PTD7
2
3
4
PTD5
PTD4/
LLWU_P14
PTC19
5
PTC14
6
PTC13
7
8
9
PTC8
PTC4/
LLWU_P8
VLL1
10
VLL2
11
VLL3 A
B
PTD10
PTD6/
LLWU_P15
PTD3
PTC18
PTC15
PTC12
PTC7
PTC3/
LLWU_P7
PTC0
PTB16
VCAP2 B
C PTD12
PTD11
PTD2/
LLWU_P13
PTC17
PTC11/
LLWU_P11
PTC10
PTC6/
LLWU_P10
PTC2
PTB19
PTB11
VCAP1 C
D PTD14
PTD13
PTD1
PTD0/
LLWU_P12
PTC16
PTC9
PTC5/
PTC1/
LLWU_P9 LLWU_P6
PTB18
PTB10
PTB8
D
E
PTD15
PTE2/
PTE1/
LLWU_P1 LLWU_P0
PTE0
VDD
VDD
VDD
PTB23
PTB17
PTB9
PTB7
E
F PTE16
PTE17
PTE6
PTE3
VDDA
VSSA
VSS
PTB22
PTB21
PTB20
PTB6
F
G PTE18
PTE19
VSS
PTE5
VREFH
VREFL
VSS
PTB3
PTB2
PTB1
PTB0/
LLWU_P5
G
ADC0_SE16/
H ADC0_DP1 ADC0_DM1 CMP1_IN2/
NC
ADC0_SE21
PTE24
PTE26
PTE4/
LLWU_P2
PTA1
PTA3
PTA17
PTA29 H
ADC1_SE16/
J ADC1_DP1 ADC1_DM1 _{CMP2_IN2/} PTA11
ADC0_SE22
PTE25
PTA0
PTA2
PTA4/
LLWU_P3
PGA0_DP/ PGA0_DM/
K ADC0_DP0/ ADC0_DM0/
ADC1_DP3 ADC1_DM3
NC
ADCCDAMMCCPP1102____SOIINNEU243T3/// ^{ADCDAMCCP001___SOINEU23T3//}
L
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
XTAL32
EXTAL32
1
2
3
4
5
VBAT
VSS
6
PTA5
PTA12
RTC_
PTA13/
WAKEUP_B LLWU_P4
7
8
PTA10
PTA14
PTA15
9
PTA16 RESET_b J
VSS
PTA19 K
VDD
PTA18 L
10
11
Figure 28. K30 121 MAPBGA Pinout Diagram
K30 Sub-Family Data Sheet, Rev. 1, 6/2012.
66
Preliminary
Freescale Semiconductor, Inc.
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