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K30P121M100SF2V2 Datasheet, PDF (35/67 Pages) Freescale Semiconductor, Inc – K30 Sub-Family
ZAS
RAS
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Pad
leakage
due to
input
protection
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
RADIN
ADC SAR
ENGINE
VADIN
VAS
CAS
INPUT PIN
INPUT PIN
INPUT PIN
RADIN
RADIN
RADIN
CADIN
Figure 10. ADC input impedance equivalency diagram
6.6.1.2 16-bit ADC electrical characteristics
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description
IDDA_ADC
fADACK
Supply current
ADC
asynchronous
clock source
Conditions1
• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
Min.
0.215
1.2
3.0
2.4
4.4
Typ.2
—
2.4
4.0
5.2
6.2
Max.
1.7
3.9
7.3
6.1
9.5
Unit
mA
MHz
MHz
MHz
MHz
TUE
Sample Time
Total unadjusted
error
See Reference Manual chapter for sample times
• 12 bit modes
—
±4
• <12 bit modes
—
±1.4
±6.8
±2.1
LSB4
DNL
Differential non-
linearity
INL Integral non-
linearity
EFS Full-scale error
• 12 bit modes
• <12 bit modes
• 12 bit modes
• <12 bit modes
• 12 bit modes
• <12 bit modes
—
±0.7 -1.1 to +1.9 LSB4
-0.3 to 0.5
—
±0.2
—
±1.0 -2.7 to +1.9 LSB4
-0.7 to +0.5
—
±0.5
—
-4
-5.4
LSB4
—
-1.4
-1.8
Table continues on the next page...
Notes
3
tADACK = 1/
fADACK
5
5
5
VADIN =
VDDA
5
K30 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
35
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