K30P121M100SF2V2 Datasheet, PDF (19/67 Pages) Freescale Semiconductor, Inc – K30 Sub-Family

Table 9. Device clock specifications (continued)
Symbol Description
f_{FlexCAN_ERCLK} FlexCAN external reference clock
f_{I2S_MCLK} I2S master clock
f_{I2S_BCLK} I2S bit clock
Min.
—
—
—
Max.
8
12.5
4
Unit
MHz
MHz
MHz
General
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I²C signals.
Table 10. General switching specifications
Symbol
Description
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ V_DD ≤ 2.7V
• 2.7 ≤ V_DD ≤ 3.6V
• Slew enabled
• 1.71 ≤ V_DD ≤ 2.7V
• 2.7 ≤ V_DD ≤ 3.6V
Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ V_DD ≤ 2.7V
• 2.7 ≤ V_DD ≤ 3.6V
• Slew enabled
• 1.71 ≤ V_DD ≤ 2.7V
• 2.7 ≤ V_DD ≤ 3.6V
Min.
1.5
100
16
100
2
—
—
—
—
—
—
—
—
Max.
—
—
—
—
—
Unit
Bus clock
cycles
ns
ns
ns
Bus clock
cycles
Notes
1, 2
3
3
3
4
12
ns
ns
6
ns
36
ns
24
5
12
ns
6
ns
36
ns
24
ns
K30 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
19
General Business Information