K30P121M100SF2V2 Datasheet, PDF (36/67 Pages) Freescale Semiconductor, Inc – K30 Sub-Family

Peripheral operating requirements and behaviors
Table 26. 16-bit ADC characteristics (V_REFH = V_DDA, V_REFL = V_SSA) (continued)
Symbol
E_Q
Description
Quantization
error
Conditions¹
• 16 bit modes
• ≤13 bit modes
Min.
—
—
Typ.²
-1 to 0
—
Max.
—
±0.5
Unit
LSB⁴
Notes
ENOB
Effective number 16 bit differential mode
of bits
• Avg=32
• Avg=4
6
12.8
14.5
—
bits
11.9
13.8
—
bits
16 bit single-ended mode
• Avg=32
• Avg=4
12.2
13.9
—
bits
11.4
13.1
—
bits
SINAD
Signal-to-noise
plus distortion
See ENOB
6.02 × ENOB + 1.76
dB
THD
Total harmonic
distortion
16 bit differential mode
• Avg=32
7
—
–94
—
dB
16 bit single-ended mode
• Avg=32
—
-85
—
dB
SFDR
Spurious free
dynamic range
16 bit differential mode
• Avg=32
7
82
95
—
dB
16 bit single-ended mode
• Avg=32
E_IL
Input leakage
error
V_TEMP25
Temp sensor
slope
Temp sensor
voltage
–40°C to 105°C
25°C
78
90
—
I_In × R_AS
—
1.715
—
—
719
—
dB
mV
mV/°C
I_In =
leakage
current
(refer to
the MCU's
voltage
and current
operating
ratings)
mV
1. All accuracy numbers assume the ADC is calibrated with V_REFH = V_DDA
2. Typical values assume V_DDA = 3.0 V, Temp = 25°C, f_ADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
4. _{1 LSB = (VREFH - VREFL)/2}^N
5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz.
K30 Sub-Family Data Sheet, Rev. 1, 6/2012.
36
Preliminary
Freescale Semiconductor, Inc.
General Business Information