K30P121M100SF2V2 Datasheet, PDF (33/67 Pages) Freescale Semiconductor, Inc – K30 Sub-Family

EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Peripheral operating requirements and behaviors
EP3
EP4
EP2
EP9
EP8
EP7
EP5
EP6
Figure 9. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 25 and Table 26 are achievable on the
differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and
ADCx_DM3.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 27 and
Table 28.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
K30 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
33
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