K30P121M100SF2V2 Datasheet, PDF (26/67 Pages) Freescale Semiconductor, Inc – K30 Sub-Family

Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol Description
Min.
FLL
f_{fll_ref}
f_dco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
640 × f_{fll_ref}
Mid range (DRS=01)
31.25
20
40
1280 × f_{fll_ref}
Mid-high range (DRS=10)
60
1920 × f_{fll_ref}
High range (DRS=11)
80
f_{dco_t_DMX32} DCO output
frequency
2560 × f_{fll_ref}
Low range (DRS=00)
—
732 × f_{fll_ref}
Mid range (DRS=01)
—
1464 × f_{fll_ref}
Mid-high range (DRS=10)
—
2197 × f_{fll_ref}
High range (DRS=11)
—
J_{cyc_fll}
t_{fll_acquire}
2929 × f_{fll_ref}
FLL period jitter
• f_VCO = 48 MHz
• f_VCO = 98 MHz
FLL target frequency acquisition time
—
—
—
PLL
f_vco
VCO operating frequency
I_pll
PLL operating current
• PLL @ 96 MHz (f_{osc_hi_1} = 8 MHz, f_{pll_ref} =
2 MHz, VDIV multiplier = 48)
48.0
—
I_pll
PLL operating current
• PLL @ 48 MHz (f_{osc_hi_1} = 8 MHz, f_{pll_ref} =
—
2 MHz, VDIV multiplier = 24)
f_{pll_ref} PLL reference frequency range
2.0
J_{cyc_pll} PLL period jitter (RMS)
• f_vco = 48 MHz
—
• f_vco = 100 MHz
—
Typ.
Max.
—
20.97
39.0625
25
41.94
50
62.91
75
83.89
100
23.99
—
47.97
—
71.99
—
95.98
—
180
—
150
—
—
1
—
100
1060
—
600
—
—
4.0
120
—
50
—
J_{acc_pll}
PLL accumulated jitter over 1µs (RMS)
• f_vco = 48 MHz
• f_vco = 100 MHz
—
1350
—
—
600
—
D_lock
Lock entry frequency tolerance
± 1.49
—
Table continues on the next page...
± 2.98
Unit
kHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ms
MHz
µA
µA
MHz
ps
ps
ps
ps
%
Notes
2, 3
4, 5
6
7
7
8
8
K30 Sub-Family Data Sheet, Rev. 1, 6/2012.
26
Preliminary
Freescale Semiconductor, Inc.
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