K30P121M100SF2V2 Datasheet, PDF (23/67 Pages) Freescale Semiconductor, Inc – K30 Sub-Family

Symbol
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
Peripheral operating requirements and behaviors
Table 14. JTAG full voltage range electricals (continued)
Description
TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
0
0
0
Max.
10
20
40
Unit
MHz
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
1/J1
—
ns
50
—
ns
25
—
ns
12.5
—
ns
TCLK rise and fall times
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
3
ns
20
—
ns
0
—
ns
—
25
ns
—
25
ns
8
—
ns
1.4
—
ns
—
22.1
ns
—
22.1
ns
100
—
ns
8
—
ns
TCLK (input)
J2
J3
J3
J4
J4
Figure 5. Test clock input timing
K30 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
23
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