K20P81M72SF1 Datasheet, PDF (66/74 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Pinout
8.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
81 80 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
MAP LQFP
BGA
E4 1 PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1 UART1_TX
E3 2 PTE1/
ADC1_SE5a ADC1_SE5a PTE1/
SPI1_SOUT UART1_RX
LLWU_P0
LLWU_P0
E2 3 PTE2/
ADC1_SE6a ADC1_SE6a PTE2/
SPI1_SCK UART1_CTS_
LLWU_P1
LLWU_P1
b
F4 4 PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN
UART1_RTS_
b
E7 — VDD
VDD
VDD
F7 — VSS
VSS
VSS
H7 5 PTE4/
DISABLED
LLWU_P2
PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX
G4 6 PTE5
DISABLED
PTE5
SPI1_PCS2 UART3_RX
E6 7 VDD
VDD
VDD
G7 8 VSS
VSS
VSS
L6 — VSS
VSS
VSS
F1 9 USB0_DP USB0_DP USB0_DP
F2 10 USB0_DM USB0_DM USB0_DM
G1 11 VOUT33 VOUT33 VOUT33
G2 12 VREGIN VREGIN VREGIN
K1 13 PGA0_DP/ PGA0_DP/ PGA0_DP/
ADC0_DP0/ ADC0_DP0/ ADC0_DP0/
ADC1_DP3 ADC1_DP3 ADC1_DP3
K2 14 PGA0_DM/ PGA0_DM/ PGA0_DM/
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3 ADC1_DM3 ADC1_DM3
L1 15 PGA1_DP/ PGA1_DP/ PGA1_DP/
ADC1_DP0/ ADC1_DP0/ ADC1_DP0/
ADC0_DP3 ADC0_DP3 ADC0_DP3
L2 16 PGA1_DM/ PGA1_DM/ PGA1_DM/
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3 ADC0_DM3 ADC0_DM3
F5 17 VDDA
VDDA
VDDA
G5 18 VREFH
VREFH
VREFH
G6 19 VREFL
VREFL
VREFL
F6 20 VSSA
VSSA
VSSA
L3 21 VREF_OUT/ VREF_OUT/ VREF_OUT/
CMP1_IN5/ CMP1_IN5/ CMP1_IN5/
CMP0_IN5/ CMP0_IN5/ CMP0_IN5/
ADC1_SE18 ADC1_SE18 ADC1_SE18
ALT5
ALT6
ALT7
EzPort
I2C1_SDA
I2C1_SCL
RTC_CLKOUT
SPI1_SIN
SPI1_SOUT
K20 Sub-Family Data Sheet, Rev. 2, 4/2012.
66
Freescale Semiconductor, Inc.