K20P81M72SF1 Datasheet, PDF (57/74 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Peripheral operating requirements and behaviors
Table 39. Master mode DSPI timing (limited voltage range) (continued)
Num
DS4
Description
DSPI_SCK to DSPI_PCSn invalid delay
DS5
DSPI_SCK to DSPI_SOUT valid
DS6
DSPI_SCK to DSPI_SOUT invalid
DS7
DSPI_SIN to DSPI_SCK input setup
DS8
DSPI_SCK to DSPI_SIN input hold
Min.
(t_BUS x 2) −
2
—
−2
15
0
Max.
—
8.5
—
—
—
Unit
Notes
ns
2
ns
ns
ns
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
DS3
DS2
DS1
DS4
DS7
DS8
First data
DS5
First data
Data
Last data
DS6
Data
Last data
Num
DS9
DS10
DS11
DS12
DS13
DS14
DS15
DS16
Figure 21. DSPI classic SPI timing — master mode
Table 40. Slave mode DSPI timing (limited voltage range)
Operating voltage
Description
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Min.
2.7
4 x t_BUS
(t_SCK/2) − 2
—
0
2
7
—
—
Max.
3.6
12.5
—
(t_SCK/2) + 2
10
—
—
—
14
14
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
K20 Sub-Family Data Sheet, Rev. 2, 4/2012.
Freescale Semiconductor, Inc.
57