K20P81M72SF1 Datasheet, PDF (23/74 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

TRACE_CLKOUT
TRACE_D[3:0]
Peripheral operating requirements and behaviors
Ts
Th
Ts
Th
Figure 5. Trace data specifications
6.1.2 JTAG electricals
Table 12. JTAG voltage range electricals
Symbol
J1
J2
J3
Description
Operating voltage
TCLK frequency of operation
• JTAG
• CJTAG
TCLK cycle period
TCLK clock pulse width
• JTAG
• CJTAG
Min.
2.7
—
—
1/J1
100
200
J4
TCLK rise and fall times
—
J5
TMS input data setup time to TCLK rise
• JTAG
53
• CJTAG
112
J6
TDI input data setup time to TCLK rise
8
J7
TMS input data hold time after TCLK rise
• JTAG
3.4
• CJTAG
3.4
J8
TDI input data hold time after TCLK rise
3.4
J9
TCLK low to TMS data valid
• JTAG
—
• CJTAG
—
J10
TCLK low to TDO data valid
—
J11
Output data hold/invalid time after clock edge¹
—
1. They are common for JTAG and CJTAG. Input transition = 1 ns and Output load = 50pf
Max.
5.5
10
5
—
—
—
1
—
—
—
—
—
—
48
85
48
3
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
K20 Sub-Family Data Sheet, Rev. 2, 4/2012.
Freescale Semiconductor, Inc.
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