K20P81M72SF1 Datasheet, PDF (28/74 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Peripheral operating requirements and behaviors
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 14. Oscillator DC electrical specifications
Symbol
V_DD
I_DDOSC
Description
Supply voltage
Supply current — low-power mode (HGO=0)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
Min.
1.71
—
—
—
—
—
—
Typ.
—
500
200
300
950
1.2
1.5
Max.
3.6
—
—
—
—
—
—
Unit
Notes
V
1
nA
μA
μA
μA
mA
mA
I_DDOSC
Supply current — high gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1
—
25
—
μA
—
400
—
μA
—
500
—
μA
—
2.5
—
mA
—
3
—
mA
—
4
—
mA
C_x
EXTAL load capacitance
C_y
XTAL load capacitance
—
—
—
2, 3
—
—
—
2, 3
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 2, 4/2012.
28
Freescale Semiconductor, Inc.