K20P81M72SF1 Datasheet, PDF (61/74 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
S1
S2
Peripheral operating requirements and behaviors
S2
S3
S4
S4
S5
S6
S9
S7
S9
S10
S7
S8
S10
S8
Figure 25. I2S/SAI timing — master modes
Table 44. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num.
S11
S12
S13
S14
S15
S16
S17
S18
S19
Characteristic
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid¹
Min.
1.71
80
45%
5.8
2
—
0
5.8
2
—
Max.
3.6
—
55%
—
—
20.6
—
—
—
25
Unit
V
ns
MCLK period
ns
ns
ns
ns
ns
ns
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K20 Sub-Family Data Sheet, Rev. 2, 4/2012.
Freescale Semiconductor, Inc.
61