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K20P81M72SF1 Datasheet, PDF (27/74 Pages) Freescale Semiconductor, Inc – K20 Sub-Family | |||
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Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Description
Min.
fdco_t_DMX3 DCO output
2
frequency
Low range (DRS=00)
â
732 Ã ffll_ref
Mid range (DRS=01)
â
1464 Ã ffll_ref
Mid-high range (DRS=10)
â
2197 Ã ffll_ref
High range (DRS=11)
â
2929 Ã ffll_ref
Jcyc_fll FLL period jitter
â
⢠fVCO = 48 MHz
⢠fVCO = 98 MHz
â
tfll_acquire FLL target frequency acquisition time
â
PLL
fvco
VCO operating frequency
48.0
Ipll
PLL operating current
⢠PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
â
2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
⢠PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
â
2 MHz, VDIV multiplier = 24)
fpll_ref PLL reference frequency range
2.0
Jcyc_pll PLL period jitter (RMS)
⢠fvco = 48 MHz
â
⢠fvco = 100 MHz
â
Typ.
23.99
47.97
71.99
95.98
180
150
â
â
1060
600
â
120
50
Max.
â
â
â
â
â
â
1
100
â
â
4.0
â
â
Unit
MHz
MHz
MHz
MHz
ps
ms
MHz
µA
µA
MHz
ps
ps
Notes
4, 5
6
7
7
8
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
⢠fvco = 48 MHz
⢠fvco = 100 MHz
8
â
1350
â
ps
â
600
â
ps
Dlock
Dunl
tpll_lock
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
± 1.49
â
± 2.98
%
± 4.47
â
± 5.97
%
â
â
150 Ã 10-6
s
9
+ 1075(1/
fpll_ref)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Îfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
K20 Sub-Family Data Sheet, Rev. 2, 4/2012.
Freescale Semiconductor, Inc.
27
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