MC9S08AW60 Datasheet, PDF (60/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Memory
4.6.4 FLASH Protection Register (FPROT and NVPROT)
During reset, the contents of the nonvolatile location NVPROT is copied from FLASH into FPROT. Bits
0, 1, and 2 are not used and each always reads as 0. This register may be read at any time, but user program
writes have no meaning or effect. Background debug commands can write to FPROT.
R
W
Reset
7
FPS7
(1)
6
FPS6
(1)
5
FPS5
(1)
4
FPS4
(1)
3
FPS3
(1)
2
FPS2
(1)
1
FPS1
(1)
This register is loaded from nonvolatile location NVPROT during reset.
0
FPDIS
(1)
1 _{Background commands can be used to change the contents of these bits in FPROT.}
Figure 4-9. FLASH Protection Register (FPROT)
Table 4-11. FPROT Register Field Descriptions
Field
Description
7:1
FPS[7:1]
0
FPDIS
FLASH Protect Select Bits — When FPDIS = 0, this 7-bit field determines the ending address of unprotected
FLASH locations at the high address end of the FLASH. Protected FLASH locations cannot be erased or
programmed.
FLASH Protection Disable
0 FLASH block specified by FPS[7:1] is block protected (program and erase not allowed).
1 No FLASH block is protected.
4.6.5 FLASH Status Register (FSTAT)
Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits
that can be read at any time. Writes to these bits have special meanings that are discussed in the bit
descriptions.
7
6
5
4
3
2
1
0
R
FCCF
0
FBLANK
0
0
FCBEF
FPVIOL FACCERR
W
Reset
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-10. FLASH Status Register (FSTAT)
MC9S08AW60 Data Sheet, Rev.1.0
60
Freescale Semiconductor