MC9S08AW60 Datasheet, PDF (130/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Internal Clock Generator (S08ICGV4)
• Clock select block — The clock select block provides several switch options for connecting
different clock sources to the system clock tree. ICGDCLK is the multiplied clock frequency out
of the FLL, ICGERCLK is the reference clock frequency from the crystal or external clock source,
and FFE (fixed frequency enable) is a control signal used to control the system fixed frequency
clock (XCLK). ICGLCLK is the clock source for the background debug controller (BDC).
8.1.1 Features
The module is intended to be very user friendly with many of the features occurring automatically without
user intervention. To quickly configure the module, go to Section 8.5, “Initialization/Application
Information” and pick an example that best suits the application needs.
Features of the ICG and clock distribution system:
• Several options for the primary clock source allow a wide range of cost, frequency, and precision
choices:
— 32 kHz–100 kHz crystal or resonator
— 1 MHz–16 MHz crystal or resonator
— External clock
— Internal reference generator
• Defaults to self-clocked mode to minimize startup delays
• Frequency-locked loop (FLL) generates 8 MHz to 40 MHz (for bus rates up to 20 MHz)
— Uses external or internal clock as reference frequency
• Automatic lockout of non-running clock sources
• Reset or interrupt on loss of clock or loss of FLL lock
• Digitally-controlled oscillator (DCO) preserves previous frequency settings, allowing fast
frequency lock when recovering from stop3 mode
• DCO will maintain operating frequency during a loss or removal of reference clock
• Post-FLL divider selects 1 of 8 bus rate divisors (/1 through /128)
• Separate self-clocked source for real-time interrupt
• Trimmable internal clock source supports SCI communications without additional external
components
• Automatic FLL engagement after lock is acquired
• External oscillator selectable for low power or high gain
8.1.2 Modes of Operation
This is a high-level description only. Detailed descriptions of operating modes are contained in
Section 8.4, “Functional Description.”
• Mode 1 — Off
The output clock, ICGOUT, is static. This mode may be entered when the STOP instruction is
executed.
MC9S08AW60 Data Sheet, Rev.1.0
130
Freescale Semiconductor