MC9S08AW60 Datasheet, PDF (129/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Internal Clock Generator (S08ICGV4)
8.1 Introduction
Figure 8-3 is a top-level diagram that shows the functional organization of the internal clock generation
(ICG) module. This section includes a general description and a feature list.
EXTAL
XTAL
V_DDA
(SEE NOTE 2)
V _SSA
(SEE NOTE 2)
ICG
OSCILLATOR (OSC)
WITH EXTERNAL REF
SELECT
ICGERCLK
FREQUENCY _DCO
LOCKED
REF
LOOP (FLL)
SELECT
CLOCK
SELECT
OUTPUT
ICGDCLK CLOCK
SELECT
IRG
INTERNAL ^{TYP 243 kHz}
REFERENCE _{8 MHz}
GENERATORS _RG
LOSS OF LOCK
AND CLOCK DETECTOR
ICGIRCLK
FIXED
CLOCK
SELECT
LOCAL CLOCK FOR OPTIONAL USE WITH BDC
/R
ICGOUT
FFE
ICGLCLK
NOTES:
1. See Table 8-1 for specific use of ICGOUT, FFE, ICGLCLK, ICGERCLK
2. Not all HCS08 microcontrollers have unique supply pins for the ICG. See the device pin assignments.
Figure 8-3. ICG Block Diagram
The ICG provides multiple options for clock sources. This offers a user great flexibility when making
choices between cost, precision, current draw, and performance. As seen in Figure 8-3, the ICG consists
of four functional blocks. Each of these is briefly described here and then in more detail in a later section.
• Oscillator block — The oscillator block provides means for connecting an external crystal or
resonator. Two frequency ranges are software selectable to allow optimal startup and stability.
Alternatively, the oscillator block can be used to route an external square wave to the system clock.
External sources can provide a very precise clock source. The oscillator is capable of being
configured for low power mode or high amplitude mode as selected by HGO.
• Internal reference generator — The internal reference generator consists of two controlled clock
sources. One is designed to be approximately 8 MHz and can be selected as a local clock for the
background debug controller. The other internal reference clock source is typically 243 kHz and
can be trimmed for finer accuracy via software when a precise timed event is input to the MCU.
This provides a highly reliable, low-cost clock source.
• Frequency-locked loop — A frequency-locked loop (FLL) stage takes either the internal or
external clock source and multiplies it to a higher frequency. Status bits provide information when
the circuit has achieved lock and when it falls out of lock. Additionally, this block can monitor the
external reference clock and signals whether the clock is valid or not.
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor
129