MC9S08AW60 Datasheet, PDF (239/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (S08ADC10V1)
Table 14-4. ADC1SC2 Register Field Descriptions (continued)
Field
5
ACFE
4
ACFGT
Description
Compare Function Enable — ACFE is used to enable the compare function.
0 Compare function disabled
1 Compare function enabled
Compare Function Greater Than Enable — ACFGT is used to configure the compare function to trigger when
the result of the conversion of the input being monitored is greater than or equal to the compare value. The
compare function defaults to triggering when the result of the compare of the input being monitored is less than
the compare value.
0 Compare triggers when input is less than compare level
1 Compare triggers when input is greater than or equal to compare level
14.4.3 Data Result High Register (ADC1RH)
ADC1RH contains the upper two bits of the result of a 10-bit conversion. When configured for 8-bit
conversions both ADR8 and ADR9 are equal to zero. ADC1RH is updated each time a conversion
completes except when automatic compare is enabled and the compare condition is not met. In 10-bit
MODE, reading ADC1RH prevents the ADC from transferring subsequent conversion results into the
result registers until ADC1RL is read. If ADC1RL is not read until after the next conversion is completed,
then the intermediate conversion result will be lost. In 8-bit mode there is no interlocking with ADC1RL.
In the case that the MODE bits are changed, any data in ADC1RH becomes invalid.
7
R
0
6
5
4
3
2
1
0
0
0
0
0
0
ADR9
ADR8
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-6. Data Result High Register (ADC1RH)
14.4.4 Data Result Low Register (ADC1RL)
ADC1RL contains the lower eight bits of the result of a 10-bit conversion, and all eight bits of an 8-bit
conversion. This register is updated each time a conversion completes except when automatic compare is
enabled and the compare condition is not met. In 10-bit mode, reading ADC1RH prevents the ADC from
transferring subsequent conversion results into the result registers until ADC1RL is read. If ADC1RL is
not read until the after next conversion is completed, then the intermediate conversion results will be lost.
In 8-bit mode, there is no interlocking with ADC1RH. In the case that the MODE bits are changed, any
data in ADC1RL becomes invalid.
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor
239