MC9S08AW60 Datasheet, PDF (105/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
6.7.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS)
In addition to the I/O control, port G pins are controlled by the registers listed below.
7
R
W
Reset
0
6
PTGPE6
5
PTGPE5
4
PTGPE4
3
PTGPE3
2
PTGPE2
1
PTGPE1
0
0
0
0
0
0
Figure 6-41. Internal Pullup Enable for Port G Bits (PTGPE)
0
PTGPE0
0
Table 6-34. PTGPE Register Field Descriptions
Field
Description
6:0
Internal Pullup Enable for Port G Bits — Each of these control bits determines if the internal pullup device is
PTGPE[6:0] enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port G bit n.
1 Internal pullup device enabled for port G bit n.
R
W
Reset
7
6
5
4
3
2
1
PTGSE6
PTGSE5
PTGSE4
PTGSE3
PTGSE2
PTGSE1
0
1
1
1
1
1
1
Figure 6-42. Output Slew Rate Control Enable for Port G Bits (PTGSE)
0
PTGSE0
1
Table 6-35. PTGSE Register Field Descriptions
Field
Description
6:0
Output Slew Rate Control Enable for Port G Bits— Each of these control bits determine whether output slew
PTGSE[6:0] rate control is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor
105