|
MC9S08AW60 Datasheet, PDF (257/320 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
|
◁ |
Chapter 15
Development Support
15.1 Introduction
This chapter describes the single-wire background debug mode (BDM), which uses the on-chip
background debug controller (BDC) module, and the independent on-chip real-time in-circuit emulation
(ICE) system, which uses the on-chip debug (DBG) module.
15.1.1 Features
Features of the BDC module include:
⢠Single pin for mode selection and background communications
⢠BDC registers are not located in the memory map
⢠SYNC command to determine target communications rate
⢠Non-intrusive commands for memory access
⢠Active background mode commands for CPU register access
⢠GO and TRACE1 commands
⢠BACKGROUND command can wake CPU from stop or wait modes
⢠One hardware address breakpoint built into BDC
⢠Oscillator runs in stop mode, if BDC enabled
⢠COP watchdog disabled while in active background mode
Features of the ICE system include:
⢠Two trigger comparators: Two address + read/write (R/W) or one full address + data + R/W
⢠Flexible 8-word by 16-bit FIFO (ï¬rst-in, ï¬rst-out) buffer for capture information:
â Change-of-ï¬ow addresses or
â Event-only data
⢠Two types of breakpoints:
â Tag breakpoints for instruction opcodes
â Force breakpoints for any address access
⢠Nine trigger modes:
â Basic: A-only, A OR B
â Sequence: A then B
â Full: A AND B data, A AND NOT B data
â Event (store data): Event-only B, A then event-only B
â Range: Inside range (A ⤠address ⤠B), outside range (address < A or address > B)
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor
257
|
▷ |