MC9S08AW60 Datasheet, PDF (206/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface (S08SPIV3)
Table 12-3. SPI1C2 Register Field Descriptions (continued)
Field
Description
1
SPISWAI
0
SPC0
SPI Stop in Wait Mode
0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI
uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the
MOSI (MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the
output driver for the single bidirectional SPI I/O pin.
0 SPI uses separate pins for data input and data output
1 SPI configured for single-wire bidirectional operation
12.3.3 SPI Baud Rate Register (SPI1BR)
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
7
6
5
4
3
R
0
0
SPPR2
SPPR1
SPPR0
W
2
SPR2
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-8. SPI Baud Rate Register (SPI1BR)
1
SPR1
0
0
SPR0
0
Table 12-4. SPI1BR Register Field Descriptions
Field
Description
6:4
SPPR[2:0]
2:0
SPR[2:0]
SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
as shown in Table 12-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
drives the input of the SPI baud rate divider (see Figure 12-5).
SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
Table 12-6. The input to this divider comes from the SPI baud rate prescaler (see Figure 12-5). The output of this
divider is the SPI bit rate clock for master mode.
Table 12-5. SPI Baud Rate Prescaler Divisor
SPPR2:SPPR1:SPPR0
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Prescaler Divisor
1
2
3
4
5
6
7
8
MC9S08AW60 Data Sheet, Rev.1.0
206
Freescale Semiconductor