FXLS8471Q Datasheet, PDF (6/75 Pages) Freescale Semiconductor, Inc – Linear Accelerometer

2
Pin Description
VDDIO 1
BYP 2
Reserved 3
SCL/SCLK 4
GND 5
16 15 14
FXLS8471Q
678
13 Reserved
12 GND
11 INT1
10 SA1/CS_B
9 INT2
Top View
16 Lead QFN-COL
3 mm x 3 mm x 1 mm
Figure 2. Pinout diagram
Table 1. Pin Description
Pin
Name
Function
1
VDDIO
Interface power supply
2
BYP
Internal regulator output bypass capacitor connection
3
Reserved
Test reserved, connect to GND
4
SCL/SCLK
I²C Serial Clock/SPI Clock
5
GND
Ground
6
SDA/MOSI
I²C Serial Data/SPI Master Out, Slave In
7
SA0/MISO⁽¹⁾
I²C address selection bit 0/SPI Master In, Slave Out
8
N/C
Internally not connected
9
INT2
Interrupt 2
10
SA1/CS_B
I²C address selection bit 1⁽²⁾/SPI Chip Select (active low)
11
INT1
Interrupt 1
12
GND
Ground
13
Reserved
Test reserved, connect to GND
14
VDD
Power supply
15
N/C
Internally not connected
16
RST
Reset input, active high. Connect to GND if unused
1. The SA0 pin is also used to select the desired serial interface mode during POR and also after a hard/soft reset event. Please see
Section 6.2.3, “I²C/SPI auto detection” for more information
2. See Table 8 for I²C address options selectable using the SA0 and SA1 pins.
Device power is supplied through the VDD pin. Power-supply, decoupling capacitors (100 nF ceramic plus 4.7 μF or larger bulk)
should be placed as close as possible to pin 14 of the device. The digital interface supply voltage (VDDIO) must also be
decoupled with a 100 nF ceramic capacitor placed as close as possible to pin 1 of the device.
The digital control signals SCL, SDA, SA0, SA1, and RST are not tolerant of voltages more than VDDIO + 0.3 V. If VDDIO is
removed, these pins will clamp any logic signals through their internal ESD protection diodes.
FXLS8471Q
6
Sensors
Freescale Semiconductor, Inc.