FXLS8471Q Datasheet, PDF (30/75 Pages) Freescale Semiconductor, Inc – Linear Accelerometer

10.1.4 TRIG_CFG (0x0A) register
FIFO trigger configuration register. After the interrupt flag of the enabled event in TRIG_CFG is set, the FIFO (when configured
in Trigger mode) is gated at the time of the interrupt event preventing the further collection of data samples. This allows the host
processor to analyze the data leading up to the event detection (up to 32 samples). For detailed information on how to utilize the
FIFO and the various trigger events, please see AN4073 available on the Freescale website.
Table 21. TRIG_CFG register
—
—
trig_trans
trig_lndprt
trig_pulse
trig_ffmt
trig_a_vecm
—
0
0
0
0
0
0
0
0
Table 22. TRIG_CFG bit descriptions
Field
trig_trans
trig_lndprt
trig_pulse
trig_ffmt
trig_a_vecm
Description
Transient interrupt FIFO trigger enable.
Landscape/Portrait orientation interrupt FIFO trigger enable.
Pulse interrupt FIFO trigger enable
Freefall/motion interrupt FIFO trigger enable
Acceleration vector-magnitude FIFO trigger enable.
10.1.5 SYSMOD (0x0B) register
Table 23. SYSMOD register
fgerr
fgt[4:0]
sysmod[1:0]
Table 24. SYSMOD bit description
Field
fgerr
fgt[4:0]
sysmod[1:0]
Description
FIFO gate error. Default value: 0.
0: No FIFO gate error detected.
1: FIFO gate error was detected.
Emptying the FIFO buffer clears the fgerr bit in the SYSMOD register.
See CTRL_REG3 [Interrupt CTRL register] (0x2C) for more information on configuring the FIFO Gate function.
Number of ODR time units since fgerr was asserted. Reset when fgerr is cleared
System mode. Default value: 0.
00: Standby mode
01: Wake mode
10: Sleep mode
The system mode register indicates the current device operating mode. Applications using the Auto-Sleep/Auto-Wake
mechanism should use this register to synchronize their application with the device operating mode. The system mode register
also indicates the status of the FIFO gate error flag and the time elapsed since the FIFO gate error flag was asserted.
FXLS8471Q
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