FXLS8471Q Datasheet, PDF (35/75 Pages) Freescale Semiconductor, Inc – Linear Accelerometer

10.1.10 CTRL_REG3 [Interrupt Control Register] (0x2C) register
Table 36. CTRL_REG3 register
fifo_gate
wake_trans wake_lndprt wake_pulse
wake_ffmt wake_en_a_vecm
ipol
0
0
0
0
0
0
0
pp_od
0
Table 37. CTRL_REG3 bit descriptions
Field
Description
fifo_gate
0: FIFO gate is bypassed. FIFO is flushed upon the system mode transitioning from Wake-to-Sleep mode or from Sleep-
to-Wake mode.
1: The FIFO input buffer is blocked when transitioning from “Wake-to-Sleep” mode or from “Sleep-to-Wake” mode until
the FIFO is flushed.⁽¹⁾ Although the system transitions from “Wake-to-Sleep” or from “Sleep-to-Wake” the contents of the
FIFO buffer are preserved, new data samples are ignored until the FIFO is emptied by the host application.
If the fifo_gate bit is set to logic ‘1’ and the FIFO buffer is not emptied before the arrival of the next sample, then the
SYSMOD[fgerr] will be asserted. The SYSMOD[fgerr] bit remains asserted as long as the FIFO buffer remains un-
emptied.
Emptying the FIFO buffer clears the SYS_MOD[fgerr] register.
wake_tran
0: Transient function is disabled in Sleep mode
1: Transient function is enabled in Sleep mode and can generate an interrupt to wake the system
wake_lndprt
0: Orientation function is disabled Sleep mode.
1: Orientation function is enabled in Sleep mode and can generate an interrupt to wake the system
wake_pulse
0: Pulse function is disabled in Sleep mode
1: Pulse function is enabled in Sleep mode and can generate an interrupt to wake the system
wake_ffmt
0: Freefall/motion function is disabled in Sleep mode
1: Freefall/motion function is enabled in Sleep mode and can generate an interrupt to wake the system
0: Acceleration vector-magnitude function is disabled in Sleep mode
wake_en_a_vecm
1: Acceleration vector-magnitude function is enabled in Sleep mode and can generate an interrupt to wake the system
The ipol The bit selects the logic polarity of the interrupt signals output on the INT1 and INT2 pins.
ipol
INT1/INT2 interrupt logic polarity:
0: Active low (default)
1: Active high
pp_od
INT1/INT2 push-pull or open-drain output mode selection. The open-drain configuration can be used for connecting
multiple interrupt signals on the same interrupt line but will require an external pullup resistor to function correctly.
0: Push-pull (default)
1: Open-drain
1. The FIFO contents are flushed whenever the system ODR changes in order to prevent the mixing of FIFO data from different ODR periods.
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FXLS8471Q
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