FXLS8471Q Datasheet, PDF (38/75 Pages) Freescale Semiconductor, Inc – Linear Accelerometer

Data Ready
Freefall/Motion Detection
Pulse Detection
Orientation Detection
Transient Acceleration Detection
Auto-Sleep
Acceleration Vector-magnitude
FIFO Interrupt
INTERRUPT
CONTROLLER
INT1
INT2
9
INT ENABLE
9
INT CFG
Figure 10. Interrupt controller block diagram
The system’s interrupt controller uses the corresponding bit field in the CTRL_REG5 register to determine the routing for the INT1
and INT2 interrupt pins. For example, if the int_cfg_drdy bit value is logic ‘0’ the functional block’s interrupt is routed to INT2, and
if the bit value is logic ‘1’ then the interrupt is routed to INT1. All interrupt signals routed to either INT1 or INT2 are logically OR’ed
together as illustrated in Figure 11, thus one or more functional blocks can assert an interrupt pin simultaneously; therefore a
host application responding to an interrupt should read the INT_SOURCE register to determine the source(s) of the interrupt(s).
SSRRCC__DRRTDSY
SRC_FF_MT
SRC_PULSE
SRC_FIFO
INT1
OR
OR ^INT2
Figure 11. INT1/INT2 PIN Control Logic
FXLS8471Q
38
Sensors
Freescale Semiconductor, Inc.