FXLS8471Q Datasheet, PDF (16/75 Pages) Freescale Semiconductor, Inc – Linear Accelerometer

6
Digital Interfaces
6.1
I²C interface characteristics
Table 7. I²C slave timing values⁽¹⁾
Parameter
Symbol
I²C Fast Mode
Min
Max
SCL Clock Frequency
Bus Free Time between STOP and START condition
(Repeated) START Hold Time
(Repeated) START Setup Time
STOP Condition Setup Time
SDA Data Hold Time
SDA Valid Time⁽³⁾
SDA Valid Acknowledge Time⁽⁴⁾
SDA Setup Time
SCL Clock Low Time
SCL Clock High Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Pulse width of spikes on SDA and SCL that must be suppressed by
internal input filter
f_SCL
t_BUF
t_HD;STA
t_SU;STA
t_SU;STO
t_HD;DAT
t_VD;DAT
t_VD;ACK
t_SU;DAT
t_LOW
t_HIGH
t_r
t_f
t_SP
0
1.3
0.6
0.6
0.6
0.05
100
1.3
0.6
20 + 0.1 C_b(5)
20 + 0.1 C_b(5)
0
400
0.9⁽²⁾
0.9⁽²⁾
0.9⁽²⁾
300
300
50
1. All values referred to VIH (min) and VIL (max) levels.
2. This device does not stretch the LOW period (t_LOW) of the SCL signal.
3. t_VD;DAT = time for Data signal from SCL LOW to SDA output.
4. t_VD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
5. C_b = total capacitance of one bus line in pF.
Unit
kHz
μs
μs
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
handbook, full pagewidth
SDA
tf
tLOW
tr
tSU;DAT
tf
tHD;STA
SCL
S
tHD;STA
tHD;DAT
tHIGH
tSU;STA
Sr
Figure 5. I²C slave timing diagram
tSP
tr
tBUF
tSU;STO
P
S
MSC610
FXLS8471Q
16
Sensors
Freescale Semiconductor, Inc.