FXLS8471Q Datasheet, PDF (39/75 Pages) Freescale Semiconductor, Inc – Linear Accelerometer

10.2 Auto-Sleep trigger
10.2.1 ASLP_COUNT (0x29) register
The ASLP_COUNT register sets the minimum time period of event flag inactivity required to initiate a change from the current
active mode ODR value specified in CTRL_REG1[dr] to the Sleep mode ODR value specified in CTRL_REG1[aslp_rate],
provided that CTRL_REG2[slpe] = 1.
See Table 45 for functional blocks that may be monitored for inactivity in order to trigger the return-to-sleep event.
Table 42. ASLP_COUNT register
aslp_cnt[7:0]
8’b00000000
Table 43. ASLP_COUNT bit description
Field
aslp_cnt[7:0] See Table 44 for details
Description
Table 44. ASLP_COUNT relationship with ODR
Output Data Rate (ODR)
800
400
200
100
50
12.5
6.25
1.56
Maximum inactivity time (s)
81
81
81
81
81
81
81
63
ODR time step (ms)
1.25
2.5
5
10
20
80
160
640
ASLP_COUNT step (ms)
320
320
320
320
320
320
320
640
Table 45. Sleep/Wake mode gates and triggers
Interrupt source
SRC_FIFO
SRC_TRANS
SRC_LNDPRT
SRC_PULSE
SRC_FFMT
SRC_ASLP
SRC_AVECM
Event restarts time and
delays Return-to-Sleep
Yes
Yes
Yes
Yes
Yes
No*
Yes
Event will Wake-from-Sleep
No
Yes
Yes
Yes
Yes
No*
Yes
* If the fifo_gate bit is set to logic ‘1’, the assertion of the SRC_ASLP interrupt does not prevent the system from transitioning to Sleep or from Wake mode; instead
it prevents the FIFO buffer from accepting new sample data until the host application flushes the FIFO buffer.
The interrupt sources listed in Table 45 affect the auto-sleep, return to sleep and wake from sleep mechanism only if they have
been previously enabled. The functional block event flags that are bypassed while the system is in Auto-Sleep mode are
temporary disabled (see Section 10.1.10, “CTRL_REG3 [Interrupt Control Register] (0x2C) register,” on page 35 for more
information) and are automatically re-enabled when the device returns from Auto-Sleep mode (that is, wakes up), except for the
data ready function.
If any of the interrupt sources listed under the Return-to-Sleep column is asserted before the sleep counter reaches the value
specified in ASLP_COUNT, then all sleep mode transitions are terminated and the internal sleep counter is reset. If none of the
interrupts listed under the Return-to-Sleep column are asserted within the time limit specified by the ASLP_COUNT register, the
system will transition to the Sleep mode and use the ODR value specified in CTRL_REG1[aslp_rate].
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Freescale Semiconductor, Inc.
FXLS8471Q
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