FXLS8471Q Datasheet, PDF (42/75 Pages) Freescale Semiconductor, Inc – Linear Accelerometer

10.4 FIFO
10.4.1 F_SETUP (0x09) register
Table 52. F_SETUP register
f_mode[1:0]
0
f_wmrk[5:0]
6b’000000
Table 53. F_SETUP bit descriptions
Field
Description
FIFO buffer operating mode.
00: FIFO is disabled.
01: FIFO contains the most recent samples when overflowed (circular buffer). Oldest sample is discarded to be replaced
by new sample.
10: FIFO stops accepting new samples when overflowed.
f_mode[1:0]^(1)(2)(3) 11: FIFO trigger mode.
The FIFO is flushed whenever the FIFO is disabled, during an automatic ODR change (Auto-Wake/Sleep), or on a
transition from Standby mode to Active mode.
Disabling the FIFO (f_mode = 2’b00) resets the F_STATUS[f_ovf], F_STATUS[f_wmrk_flag], F_STATUS[f_cnt] status
flags to zero.
A FIFO overflow event (that is, F_STATUS[f_cnt] = 32) will assert the F_STATUS[f_ovf] flag.
f_wmrk[5:0]⁽²⁾
FIFO sample count watermark.
These bits set the number of FIFO samples required to trigger a watermark interrupt. A FIFO watermark event flag
F_STATUS[f_wmk_flag] is raised when FIFO sample count F_STATUS[f_cnt] value is equal to or greater than the
f_ wmrk watermark.
Setting the f_wmrk to 6’b000000 will disable the FIFO watermark event flag generation.
This field is also used to set the number of pre-trigger samples in trigger mode (f_mode = 2’b11).
1. This bit field can be written in Active mode.
2. This bit field can be written in Standby mode.
3. The FIFO mode (f_mode) cannot be switched between operational modes (01, 10 and 11).
A FIFO sample count exceeding the watermark event does not stop the FIFO from accepting new data.
The FIFO update rate is dictated by the selected system ODR. In Active mode the ODR is set by CTRL_REG1[dr] and when
Auto-Sleep is active, the ODR is set by CTRL_REG1[aslp_rate] bit fields.
When data is read from the FIFO buffer, the oldest sample data in the buffer is returned and also deleted from the front of the
FIFO, while the FIFO sample count is decremented by one. It is assumed that the host application will use the I²C or SPI burst
read transactions to dump the FIFO contents. If the FIFO X, Y, and Z data is not completely read in one burst read transaction,
the next read will start at the next FIFO location X-axis data. If the Y or Z data is not read out in the same burst transaction as
the X-axis data, it will be lost.
In Trigger mode, the FIFO is operated as a circular buffer and will contain up to the 32 most recent acceleration data samples.
The oldest sample is discarded and replaced by the current sample, until a FIFO trigger event occurs. After a trigger event occurs,
the FIFO will continue to accept samples only until overflowed, after which point the newest sample data is discarded. For more
information on using the FIFO buffer and the various FIFO operating modes, please refer to Freescale application note AN4073.
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