FXLS8471Q Datasheet, PDF (41/75 Pages) Freescale Semiconductor, Inc – Linear Accelerometer

10.3 Output data registers
10.3.1 OUT_X_MSB (0x01), OUT_X_LSB (0x02), OUT_Y_MSB (0x03), OUT_Y_LSB (0x04),
OUT_Z_MSB (0x05), OUT_Z_LSB (0x06) registers
These registers contain the X-axis, Y-axis, and Z-axis 14-bit left-justified sample data expressed as 2's complement numbers.
The sample data output registers store the current sample data if the FIFO buffer function is disabled, but if the FIFO buffer
function is enabled the sample data output registers then point to the head of the FIFO buffer which contains up to the previous
32 X, Y, and Z data samples.
The data is read out in the following order: Xmsb, Xlsb, Ymsb, Ylsb, Zmsb, Zlsb for CTRL_REG1[f_read] = 0, and Xmsb, Ymsb,
Zmsb for CTRL_REG1[f_read] = 1. Similarly, for CTRL_REG1[f_read] = 1, only the MSB's of the acceleration data are read out
in the same axis order.
If the CTRL_REG1[f_read] bit is set, auto-increment will skip over the LSB registers. This will shorten the data acquisition from
6 bytes to 3 bytes. If the LSB registers are directly addressed, the LSB information can still be read regardless of the
CTRL_REG1[f_read] register setting.
If the FIFO data output register driver is enabled (F_SETUP[f_mode] > 00), register 0x01 points to the head of the FIFO buffer,
while registers 0x02, 0x03, 0x04, 0x05, 0x06 return a value of zero when read directly.
The DR_STATUS registers, OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB are
located in the auto-incrementing address range of 0x00 to 0x06, allowing all of the acceleration data to be read in a single-burst
read of 6 bytes starting at the OUT_X_MSB register.
Table 46. OUT_X_MSB register
xd[13:6]
Table 47. OUT_X_LSB register
xd[5:0]
—
—
Table 48. OUT_Y_MSB register
yd[13:6]
Table 49. OUT_Y_LSB register
yd[5:0]
—
—
Table 50. OUT_Z_MSB register
zd[13:6]
Table 51. OUT_Z_LSB register
zd[5:0]
—
—
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FXLS8471Q
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