K20P48M50SF0 Datasheet, PDF (46/60 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Peripheral operating requirements and behaviors
Table 31. USB VREG electrical specifications
(continued)
Symbol Description
C_OUT
ESR
External output capacitor
External output capacitor equivalent series
resistance
I_LIM
Short circuit current
Min.
1.76
1
—
Typ.¹
2.2
—
290
Max.
8.16
100
—
Unit
Notes
μF
mΩ
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I_Load.
6.8.4 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 32. Master mode DSPI timing (limited voltage range)
Num
DS1
DS2
DS3
Operating voltage
Description
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DS4
DSPI_SCK to DSPI_PCSn invalid delay
DS5
DSPI_SCK to DSPI_SOUT valid
DS6
DSPI_SCK to DSPI_SOUT invalid
DS7
DSPI_SIN to DSPI_SCK input setup
DS8
DSPI_SCK to DSPI_SIN input hold
Min.
Max.
2.7
3.6
—
25
2 x t_BUS
—
(t_SCK/2) − 2 (t_SCK/2) + 2
(t_BUS x 2) −
—
2
(t_BUS x 2) −
—
2
—
8
0
—
14
—
0
—
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
2
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
46
Freescale Semiconductor, Inc.