K20P48M50SF0 Datasheet, PDF (38/60 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Peripheral operating requirements and behaviors
Table 24. 16-bit ADC characteristics (V_REFH = V_DDA, V_REFL = V_SSA) (continued)
Symbol Description
f_ADACK
ADC
asynchronous
clock source
Conditions¹
• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
Min.
1.2
3.0
2.4
4.4
Typ.²
2.4
4.0
5.2
6.2
Max.
3.9
7.3
6.1
9.5
Unit
MHz
MHz
MHz
MHz
Notes
t_ADACK = 1/
f_ADACK
Sample Time
See Reference Manual chapter for sample times
TUE
Total unadjusted
error
• 12 bit modes
• <12 bit modes
—
±4
±6.8
LSB⁴
5
—
±1.4
±2.1
DNL
Differential non-
linearity
INL Integral non-
linearity
E_FS
Full-scale error
E_Q
Quantization
error
• 12 bit modes
• <12 bit modes
• 12 bit modes
• <12 bit modes
• 12 bit modes
• <12 bit modes
• 16 bit modes
• ≤13 bit modes
—
±0.7
-1.1 to
LSB⁴
5
+1.9
—
±0.2
-0.3 to 0.5
—
±1.0
-2.7 to
LSB⁴
5
+1.9
—
±0.5
-0.7 to
+0.5
—
-4
-5.4
LSB⁴
V_ADIN =
—
-1.4
-1.8
V_DDA
5
—
-1 to 0
—
LSB⁴
—
—
±0.5
ENOB
Effective number 16 bit differential mode
of bits
• Avg=32
• Avg=4
6
12.8
14.5
—
bits
11.9
13.8
—
bits
16 bit single-ended mode
• Avg=32
• Avg=4
12.2
13.9
—
bits
11.4
13.1
—
bits
SINAD
Signal-to-noise
plus distortion
See ENOB
6.02 × ENOB + 1.76
dB
THD
Total harmonic
distortion
16 bit differential mode
• Avg=32
7
—
–94
—
dB
16 bit single-ended mode
• Avg=32
—
-85
—
dB
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
38
Freescale Semiconductor, Inc.